1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device for preventing plasma-induced damage (PID).
2. Description of the Related Art
Semiconductor devices are highly integrated and continue to get smaller and smaller. The shrinking technology means the space between patterns formed on the surface of a wafer also shrinks, and the aspect ratio increases. Here, new issues in semiconductor manufacturing and fabrication processes arise.
For example, issues arise in a fabrication process using plasma. More specifically, as a deposition process or an etch process is performed using plasma, plasma-induced damage (PID) occurs and deteriorates some properties of a semiconductor device.
PID is the damage occurring in a semiconductor fabrication process using plasma, and it occurs because plasma contains ions that discharge charges into a wafer through an interaction between the plasma ions and the wafer.
There are many factors that affect PID, such as ions that are formed as plasma and ultraviolet radiation. Particularly, charging of a wafer with ions is known as a major factor for PID.
FIGS. 1 and 2 illustrate PID occurring in conventional technology.
Referring to FIG. 1, a source gas is supplied and plasma is generated in deposition and etching processes that use plasma, and there are excited molecules, radicals, ions Ji, and electrons Je in the generated plasma. The electrons Je and the ions Ji have predetermined energy levels and enter a wafer 100. Here, the amount of electrons Je and ions Ji that enter the wafer 100 are the same, but due to a difference in distribution speed, almost all of the ions Ji enter the surface of the wafer 100 vertically, and the electrons Je enter the surface of the wafer 100 at predetermined angles. During this process, when there is no structure, such as a pattern, on the wafer 100, both the ions Ji and the electrons Je enter the wafer and the wafer 100 maintains a balanced charge. However, when there is a pattern, the charge balance between the ions Ji and the electrons Je is broken.
More specifically, as illustrated in FIG. 2, when there is a pattern 210 on a wafer 200, most ions Ji enter the surface of the wafer 200 vertically. However, the entering path of the electrons Je is obstructed by the pattern 210 and the electrons Je do not enter through the pattern 210 but are reflected out. Therefore, the number of electrons Je entering the wafer 200 between the patterns 210 is decreased. As a result, the amount of the electrons Je entering the sidewalls of the pattern 210 is more than the amount of the ions Ji, and the sidewalls of the upper portion of the pattern 210 are charged with negative (−) charges. Also, the surface of the wafer 200 between the patterns 210 is charged with positive (+) charges from the ions Ji. This charging effect becomes more evident as a device is highly integrated and the patterns 210 are formed more delicately. Accordingly, when the wafer 200 is electrically isolated, the sidewalls of the pattern 210 are charged with negative (−) charges due to the electrons Je, while the portion where the pattern 210 meets the surface of the wafer 200 is charged with positive (+) charges.
Also, a spatial uniformity of the plasma varies according to the environment of a piece of equipment or a plasma condition, and thus the charging density of the wafer 200 is further imbalanced.
The deposition and etching processes using plasma are mostly performed on the surface of a non-conductive material, such as a dielectric material, e.g., silicon oxide (SiO2). As a non-uniform charging density is formed in the wafer 200 and the pattern 210 in the way described above, a current is generated that flows from a portion with high charging density to a portion with low charging density as a reaction to the non-uniform charging density. The current flows through a device inside of the wafer, for example, in a gate insulation layer, so as to apply an electrical stress to a semiconductor device. This generated current also causes PID, such as an electron trap and a leakage current path inside of the gate insulation layer.
More specifically, a field strong to a thin metal line is formed due to the non-uniform charging density, and because of the strong field, the metal line becomes molten.
Also, a potential level difference between a gate and a bulk is raised due to the strong field and a gate oxide layer may be damaged.
Moreover, the non-uniform charging density affects a threshold voltage of a transistor and changes the properties of the transistor.
According to a conventional technology for preventing the PID, any non-uniform charging density is addressed by inserting a protective diode to provide the ions with an artificial path through which the ions may be drained. According to the conventional technology, when a well area is large, a protective diode is formed for each transistor region.
FIG. 3 is a layout illustrating a conventional semiconductor device with a PID protective diode inserted thereto.
Referring to FIG. 3, a path through which charges may be drained is formed as a gate electrode 32 of a transistor region Tr1 to be protected from PID is coupled with a diode 34 in the conventional semiconductor device with a PID protective diode inserted thereto.
More specifically, the transistor region Tr1 and a well guard 31 of a structure surrounding the transistor region Tr1 are disposed over a well 30. The well guard 31 is disposed on the boundaries of the well 30 and circuits inside of the well guard 31 constitute one circuit block. The well guard 31 prevents a latch-up from occurring among adjacent circuit blocks. A bias of a predetermined level is applied as a pick-up and is formed in the well guard 31.
A gate electrode 32 is formed over the transistor region Tr1, and the diode 34 is disposed to be spaced apart from the transistor region Tr1 by a space S.
A metal line 33 is disposed over an upper layer of the diode 34 to overlap with the diode 34. The metal line 33 is coupled with the gate electrode 32 through a contact plug CG, and coupled with the diode 34 through a contact plug CD.
According to the conventional technology, however, the layout area is greatly increased in size due to the disposition of the protective diode 34. This increase in layout area size tends to prevent further integration.
As shown in FIG. 3, when independent transistor regions Tr2 and Tr3 are disposed on the right and left sides of the transistor region Tr1, a space between transistor regions Tr1 and Tr2 is greater than a space between transistor regions Tr1 and Tr3 because of the disposition of the diode 34. A space between transistor region Tr1 and transistor region Tr3 corresponds to a space S. Whereas the space between transistor regions Tr1 and Tr2 corresponds to S, a space between the diode 34 and the transistor region Tr1, S, a space between transistor region Tr2 and the diode 34, plus a width W of the diode 34. This additional space for placing the diode 34 prevents further integration of the semiconductor device.
Therefore, it is useful to efficiently dispose a PID protective diode in order to increase the integration degree of the semiconductor device.